module mux4x16_tb (
    
);

reg [15:0] a0,a1,a2,a3;
reg [1:0] mux;
wire [15:0] q;

initial begin
    a0 = 1;
    a1 = 2;
    a2 = 3;
    a3 = 4;
    #10 mux = 0;
    #10 mux = 1;
    #10 mux = 2;
    #10 mux = 3;
    #10 $finish;
end

initial begin
    $dumpfile("wave.vcd");
    $dumpvars( );
end

mux4x16 u_mux4x16(
    .a0  (a0  ),
    .a1  (a1  ),
    .a2  (a2  ),
    .a3  (a3  ),
    .mux (mux ),
    .q   (q   )
);

    
endmodule